Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
USB2 Controller | Cadence
Difference between USB and ULPI - Electrical Engineering Stack Exchange
USB3250 | Microchip Technology
USB 2.0 PHY IP Core Device Host OTG Hub in TSMC, 28HPC, 40LP /LL, UMC, 40LP, 28HPC, SMIC 14SF, SF, 55LL, 40LL - T2M-IP
USBPHYC internal peripheral - stm32mpu
USB Component: USB Device
PhyWhisperer-USB - NewAE Hardware Product Documentation
PCIe/USB/SATA PHY Application Example | Renesas
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
USB 2.0 PHY IP core | Arasan Chip Systems
USB2 PHY | Cadence
USB 2.0 PHY IP Core
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
Synopsys IP Technical Bulletin: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
Figure 1 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 2.0 Full High Speed Solution | NXP Semiconductors
Synopsys IP Technical Bulletin: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
USB2.0 PHY – Silicon Library Inc.
Hi-Speed USB interfacing
Usb3300 Usb Hs Board Host Otg Phy Low Pin Ulpi Evaluation Development Module Kit - Integrated Circuits - AliExpress
PhyWhisperer-USB | Crowd Supply
Mixed-Signal Verification for USB 2.0 Physical Layer IP
USB v2.0 Soft PHY and Device Controller
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
